1. Field of the Invention
The present invention relates to a semiconductor package, and more particularly to a semiconductor package capable of freely coping with various package types such as a SOJ type, ZIP type and etc. without changing the type of a semiconductor chip to be used, upon packaging a highly integrated memory of a 16-mega-bit grade or greater and improving the degree of freedom in designing a layout of the pads of semiconductor chip, thereby improving the characteristic of a semiconductor device to be manufactured and the degree of integration.
2. Description of the Prior Art
Generally, a semiconductor package is made by wire-bonding inner leads of a lead frame to corresponding pads of a semiconductor chip and then molding the semiconductor chip using a resin material.
FIG. 1 is a plan view showing the connection between a semiconductor chip and a lead frame in a semiconductor package of a general small outline J bend (SOJ) type. FIG. 2 is a sectional view of a typical example of such a general SOJ type semiconductor package. As shown in the drawings, the semiconductor chip which is denoted by the reference numeral 3 is attached to a paddle 2 of the lead frame 1, by means of an epoxy adhesive 8. The semiconductor chip 3 has a plurality of pads 4 including pads 4a, 4b and 4c which are connected with inner leads 5 of the lead frame 1 by means of wires 6. The semiconductor chip 3 and the inner leads 5 of the lead frame 1 are molded with an epoxy resin 7.
In such a SOJ type semiconductor package, the semiconductor chip 3 has a source pad 4a at the lower end of one side portion thereof and a ground pad 4b at the upper end of the other side portion thereof, as shown in FIG. 2. The reference numeral 4c denotes general pads for inputting and outputting signals.
For wire-bonding the inner leads 5 of lead frame 1 to the corresponding pads 4 formed on the semiconductor chip 3 by means of metal wires 6, a layout for the semiconductor chip 3 is designed to allow the space between each inner lead 5 of the lead frame 1 and each corresponding pad 4 of the semiconductor chip 3 to be not more than 200 MIL (1 MIL=1/1000 inch).
For the same purpose, it is also necessary to provide a design space allowing each inner lead of the lead frame to be designed to correspond to the position at which each corresponding pad is formed. For example, in semiconductor packages of a 16-mega-bit DRAM grade, such a design space should be not less than 50 MIL in both X-axis and Y-axis directions.
The outline size of semiconductor package is also fixed for providing a compatibility of the semiconductor package. For example, semiconductor packages of the 16-mega-bit DRAM grade have the outline size of 400 mm.times.725 mm. As a result, in case of a small-sized semiconductor chip, pads are formed at corner portions of the semiconductor chip. In this case, a lead frame is designed such that its inner leads correspond to the pads formed at the corner portions of semiconductor chip, so as to be wire-bonded thereto.
In case of a highly integrated semiconductor chip of the 16-mega-bit DRAM grade or greater, that is, a large-sized semiconductor chip, in particular, in case of a SOJ type semiconductor package having outer leads protruded from its opposite sides as shown in FIGS. 1 and 2, pads 4 are formed at opposite side edges of the semiconductor chip and are wire-bonded to the corresponding inner leads 5 arranged at opposite sides of the lead frame 1. On the other hand, in case of a semiconductor package of a zigzag inline package (ZIP) type, pads are formed at the corner portions of the semiconductor chip by using option pads, so as to cope with a variation in the type of package.
In such conventional packages with the above-mentioned structures, electric power is supplied to an internal circuit of the semiconductor chip 3 via specific outer leads of the lead frame 1, that is, a source terminal Vcc and a ground terminal Vss. Via the remaining outer leads, that is, signal terminals, signal inputting and outputting are carried out between the internal circuit of the semiconductor chip 3 and the external of the package.
Typically, the positions of source terminal Vcc and ground terminal Vss which are specific outer leads of the semiconductor package are fixed. As a result, the positions of source pad and ground pad are also fixed, to which inner leads connected to the source terminal Vcc and ground terminal Vss are wire-bonded. In case of the SOJ type semiconductor package, therefore, the source pad and the ground pad are formed at the lower end of one side portion and the upper end of the other side portion of semiconductor chip.
Such a limitation on the positions of source pad and ground pad becomes a factor of limiting the design of semiconductor chips. On the other hand, source lines made of metal are disposed in the semiconductor chip and connected in parallel to various internal circuit parts, so as to supply electric power thereto. These source lines have various and long lengths, thereby causing the degree of freedom in designing the semiconductor chip to be very limited. They also effect adversely an accurate supplying of static voltage to each internal circuit part. Since the source lines also have a width very larger than those of other signal lines, they occupy a great area in the semiconductor chip, if their length increases. As a result, there are problems of degrading the degree of integration and requiring an increase in chip area. The arrangement of various source lines also becomes a factor of generating a noise. The increased length of source lines results in a decrease in speed, thereby causing the performance of semiconductor chip to be degraded.
Where both a SOJ type package and a ZIP type package are to be made with semiconductor chips of the same kind, there is no problem when the chips have a small size. In case of the semiconductor chips having a large size, however, there is a problem that pad positions for the SOJ type package should be designed differently from those for the ZIP type package.